vscode-systemverilog-support
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mshr-h
[deprecated]use mshr-h/vscode-verilog-hdl-support
Hi, when i installed the extension, and i set "editor.tabCompletion": true, the key tab isn't working. Which is pressing tab in editor does nothing, but what i want is a...
Processing of a class declaration only allow spaces prior to the keyword 'class'. This doesn't allow for detection of virtual classes. Consider changing the following regex ^\s*(module|function|primitive|class|package|constraint... To ^\s*(?:virtual\s+(?=class))? (module|function|primitive|class|package|constraint......
It seems like there is no syntax highlighting of the keyword 'let' so far, am I right? Is there a reason for that? The construct is described in IEEE Std...
The alignment formatting has several features that may or may not be welcome depending on the user's coding standard. Possible formatting disagreements - [ ] Aligning semicolons at the end...
A few weeks ago, when I write sv file using this package, it can match the every `begin` that I type with `end` pair. However, now I found this feature...
Is there a way to fix the begin end matching problem now? It seems like there is no auto-matching for them supported. Its really a pain to visually match each...
When aligning the ports of a module, the end of line gets semicolons added. ```systemverilog input logic clk, input logic we_n, input logic cas_n, input logic ras_n, input logic cs_n,...