vscode-systemverilog-support
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[deprecated]use mshr-h/vscode-verilog-hdl-support
Hi, I started used your extension for systemverilog code and for what I could observed some functions on systemverilog are not highlight. I hope you can add these functions to...
While using instantiate module command, interfaces in the module will be ignored. For example, if the definition of the module is: ``` module even_top ( input clk, reset, flush, flush_include_3rd,...
Hi, Is autoindent supported. If so, how to turn it on? Thanks, Siarhei
Thanks for sharing this extension! There is a bug when using replication operator  We find out that when using replication operator, only the second left-brace is highlighted.
The hover functionality does not work when working with custom types. ```systemverilog typedef enum logic [1:0] { FIXED = 2'b00, INCR = 2'b01, WRAP = 2'b10 } BurstType; BurstType wburst_type;...
First thank you for developing this extension! It really saves a lot of time while coding system verilog. Is there any plan to add the snippets support for this extension?...