vscode-systemverilog-support
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begin end matching
Is there a way to fix the begin end matching problem now? It seems like there is no auto-matching for them supported. Its really a pain to visually match each of them
It seems that it was supported until this commit: https://github.com/mshr-h/vscode-systemverilog-support/commit/9cecec588ae1d0a833f8d06f7e1e7afe34b270c2
Not sure why it was removed...
Ok, just tried it by re-adding ["begin", "end"] to the brackets list, and it kinda works.
Kinda, because there a few issues with other "end" keywords, like endcase, endgenerate and endmodule which are also detected as simple "end".
However, I have a feeling this has to be fixed/handled in the core of VS Code and can't be fixed in the extension. :/
It's already discussed in #6.