Matteo Perotti

# Update CVA6 and FPU. CVA6 now has half of the L1 caches. In the future, we will probably go for the same size, but with doubled cache lines and...

The previous mechanism to handle the commit during a reduction was confusing and led to bugs. Now, the reduction triggers its commit only after the inter-lanes phase is over. Also,...

[hardware] Floating-Point classify, division, sqrt

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# This PR depends on https://github.com/pulp-platform/ara/pull/133 and, for ease of merging, on https://github.com/pulp-platform/ara/pull/131 as well Add floating-point classify, division, sqrt instructions, delayed because of the FPU. I updated the CVA6...

# This PR depends on https://github.com/pulp-platform/ara/pull/133 This PR introduces FP-reduction support to Ara. Thanks to @xiaorui-yin for the great work and effort! ## Changelog ### Added - Support for vector...

Add support for vector floating-point division and square-root instructions

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Currently, Ara supports the most important FP operations to run a `matmul` kernel. All the other vector floating-point instructions still need to be added. Note: Some of them, namely: -...

# Reminder issue `emul` checks are done using `ara_req_d.emul`. This is not correct if one of the source operands has different `emul` w.r.t. the other source or destination register. Easy...

Write requests from SLDU/MASKU/VLSU have low priority wrt requests from the computational FUs and operand queues. The request of one of the low priority units to the operand requesters is...

Multiple operations on the same `vd`, with different `VSEW` and `vl`

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The following operation does not work on Ara. > VSET(1, e64, m1); VLOAD_64(v1, 0xffffffffffffffff); VSET(16, e16, m1); VLOAD_16(v2, 0x33ca, ..., 0x314f); VLOAD_16(v3, 0x33ca, ..., 0xbb98); asm volatile("vmfeq.vv v1, v2, v3");...

Test different Ara parameters and instruction combinations

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One of the ways in which Ara is currently verified is by running `rv64uv` tests following the `riscv-tests` approach (https://github.com/riscv/riscv-tests), i.e., verifying each instruction with ad-hoc tests exploiting common macros....

Description of PR that completes issue here... ## Changelog ### Fixed - Description of changes ### Added - Description of changes ### Changed - Description of changes ## Checklist -...