[hardware] :arrow-up: CVA6 update: half$, FPU, bugs

[mp-17]

Update CVA6 and FPU.

CVA6 now has half of the L1 caches. In the future, we will probably go for the same size, but with doubled cache lines and half lines. We fixed a de-synchronization bug in the FPU and added a classify feature that more resembles the one needed by the vector specs. We also fixed CVA6's ability to track commit fp-registers when Ara should answer back with a scalar fp value.

Changelog

Fixed

• Fixed de-synch bug in vector-FPU
• CVA6 tracks writes to floating-point scalar registers by the accelerator

Changed

• Halve CVA6's L1 caches to ease backend timing closure
• Remove CVA6's cache-patch

Checklist

• [x] Automated tests pass
• [x] Changelog updated
• [x] Code style guideline is observed