Operand Requester early grant to SLDU/MASKU/VLSU

[mp-17]

Write requests from SLDU/MASKU/VLSU have low priority wrt requests from the computational FUs and operand queues. The request of one of the low priority units to the operand requesters is buffered into a stream register (FIFO). The request is granted by default if the FIFO is not full. But the actual VRF write can be delayed indefinitely if higher priority requests are made to the same VRF bank. This leads to RAW constraints violations, as the early grant unset the instruction ID from the running instructions, also clearing the hazards bits of the dependant instructions that are free to execute, possibly fetching their operand before the write of the low priority request occurs.

Here a little example:

0: vslide1down X, Y 1: vfmul Z, X

The vfmul gets the hazard bit on instruction 0 and stalls, waiting for 0 to write X. The sldu fires a request to the operand requesters, and it immediately gets the gnt from the stream registers (the gnt is always asserted). The problem is that the real request to the VRF is not done, and it is not sure when it will happen (because of the priority arbiters; e.g., our request is delayed because a VFMUL is reading from bank 0, another VFMUL wants to write in bank0, interleaved). In the meantime, the sldu received the grant, so it tells the main sequencer that its instruction is over. So the hazards bits for the vfmul are cleared, and the vfmul can violate the RAW hazard if the write by the slide unit did not happen.