Max Korbel
Max Korbel
### Motivation The `SimCompare` utility generates messages like "expected y=1'bx but found..." in the generated SV testbenches. This is inaccurate for multi-bit invalid signals. This is not a functional problem,...
### Motivation See https://github.com/intel/rohd/discussions/363 It might be nice to assign part of a signal conditionally. ### Desired solution A function on `Logic` which could do a partial set (maybe similar...
### Motivation There are known bugs with "unpacked" arrays in SystemVerilog. For example: - Assigning: - - - Single-element unpacked: - The ROHD test-suite relies on SystemVerilog simulators to verify...
### Motivation Many repos have code coverage metrics provided in two places automatically: - On the README as a badge, indicating coverage for the repo by the test suite. -...
### Motivation There are some scenarios where creating latches is valuable (`always_latch`). ### Desired solution Add a way to generate latches to ROHD. Perhaps as a sibling or configuration of...
### Describe the bug It is possible to set up port connectivity between two `Module`s such that after `build` each of the modules have the other listed as a sub-module...
### Motivation Sometimes a "top" level module is purely for integration purposes (e.g. for testbench purposes, or early in development), and so it has no external top-level ports. In this...
### Motivation As it is currently implemented, whenever there is an `Exception` thrown via `Simulator.throwException`, the `Simulator.run` function will always throw the first exception and halt any remaining progress through...
### Motivation Sometimes an X appears in simulation in an unexpected way, and it can be difficult to trace to the root cause if there's no clear X coming into...
## Description & Motivation If the output of one Sequential is used as a clock trigger to another Sequential, the phased simulator can sometimes detect the edge and drive the...