Fix bug related to clock divider simulation, fix #191

[mkorbel1]

Description & Motivation

If the output of one Sequential is used as a clock trigger to another Sequential, the phased simulator can sometimes detect the edge and drive the outputs of the downstream Sequential one tick late.

This is because there was a gate in the Sequential clock sampling logic that ignored clock toggles during the clkStable phase. Instead, we should immediately execute the flop if we're already in clkStable.

Related Issue(s)

Fix #191

Testing

Added a new test where two counters are driven by an original clock and that clock divided, respectively.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

[mkorbel1]

Consider adding a async-reset clk-div testcase.

Added in latest commit, good idea, thanks

[mkorbel1]

Need to add more testing around chains of clock dividers, which are broken with current implementation in this PR. Likely solution is to use topological sort to pick the order of Sequential execution.