Max Korbel
Max Korbel
## Motivation There are cases where you want to compare two `LogicValues` values for some bits, but not all bits. It would be nice to support an equality check that...
## Motivation It would be nice to use `FlipFlop` with a reset signal (optionally synchronous or asynchronous) ## Desired solution Add optional named parameter(s) to `FlipFlop` that, when specified, add...
## Motivation SystemVerilog assertions are valuable for design and verification. It would be nice to have assertions in ROHD that give similar functionality, but that are also "synthesizable" to behavioral...
**Is your feature request related to a problem? Please describe.** ROHD interfaces already support hierarchical interfaces, but there is no documentation or examples covering how to do it. **Describe the...
It would be nice to have a mixin that lets ROHD know it will fail to synthesize a `Module`. That way if an architectural model or BFM has a `Module`...
Right now, `Module` has a method `generateSynth` which uses a `SynthBuilder` and `SystemVerilogSynthesizer` to generate SystemVerilog file contents. It would be better if `Synthesizer` had a function that consumes `Module`s...
The default implementation for `If`, `Iff`, etc. take lists of `Conditional`s as inputs, which can be excessively verbose in cases where there is only one `Conditional`. Adding a special constructor...
Similar to SystemVerilog: http://www.verilogpro.com/systemverilog-unique-priority/
Useful for assembly of components, analog/MSV, etc.
A convenient operation to check if one `Logic` is currently equal to any of a list of other `Logic`s, which synthesizes safely to hardware. The operation could be called `equalsAnyOf`...