Add support for behavior similar to and conversion to SystemVerilog's `inout`

[mkorbel1]

Useful for assembly of components, analog/MSV, etc.

[mkorbel1]

Since Logics have an underlying Wire, this might not be too hard to implement. Basically instead of assigning with a single srcConnection, there has to be a way to connect multiple Logics so that they share the same Wire without blocking the srcConnection or checking that it isn't already connected, then the value would propagate everywhere. We still need a way to trace connectivity (like finding all those merged Logics) for building purposes.

Module would need a way to addInOut in addition to inputs and outputs.

Simulation of driving a signal would have to comprehend if there are multiple active drivers on a signal and generate X's appropriately. It would be good to think through mechanisms for safely modelling circuits that drive and receive on inout ports and signals with multiple drivers.