Max Korbel
Max Korbel
### Motivation There's currently no way to swizzle or grab a subset of a `LogicNet` (or similarly array net) and have the result also be a net that is capable...
### Motivation The "pair_interface_test.dart" is currently the best place for documentation related to `driveOther`, `receiveOther`, `conditionalDriveOther`, and `conditionalReceiveOther`. It would be good to have them in the user guide as...
### Motivation Currently all the `Swizzle` and `swizzle` stuff operates/extensions on `List`s. Why not on `Iterable` so people don't need to do `.toList()` before accessing it? ### Desired solution Make...
### Motivation If you `signExtend` by 1 bit, you end up with a `1{...}`, which is unnecessarily verbose in generated SystemVerilog. The `replicate` function has the same thing. ### Desired...
### Motivation These are useful utilities and it's not easy enough to discover them. ### Desired solution Perhaps in the `logic-arrays` part of the user guide, add some discussion of...
### Motivation When using the base `PairInterface.clone`, it would be nice if by default it also cloned any `subInterfaces`. ### Desired solution Upgrade `PairInterface.clone` to clone `subInterfaces` as well. ###...
### Motivation The underlying modules for some convenience functions like `flop`, `cases`, and `mux` have arguments for `name`, but the functions themselves do not. It would be nice to expose...
### Motivation When running many tests, it may be necessary to build many versions of the same or different `Module`s, each with a variety of their own `Logic`s. The `_Wire`s...
### Motivation There's a lot of different ways to build hardware, especially reusable/configurable components. A cookbook/guide on best practices, trade-offs, etc. would be very helpful for new users. ### Desired...
## Description & Motivation There were cases where an error could occur during simulation and the simulation would not indicate that it had ended. This PR fixes those bugs and...