When replicating by 1, just return the 1 signal

[mkorbel1]

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Motivation

If you signExtend by 1 bit, you end up with a 1{...}, which is unnecessarily verbose in generated SystemVerilog.

The replicate function has the same thing.

Desired solution

Make it so that Logic.replicate, when multiplier is 1, just returns the same thing.

Make it so Logic.signExtend uses replicate (instead of directly ReplicationOp), so that it gets the same benefit.

Alternatives considered

No response

Additional details

No response