Max Korbel

Testing for 0-width ports it blocked pending https://github.com/intel/rohd/issues/57. Some code for testing it is already started in cosim_test.dart.

There are some scenarios where ROHD Cosim will send multiple ticks to the SV simulator back-to-back without any additional value added (e.g. I think if there are no events in...

There can be situations where the SystemVerilog simulator needs to tick multiple times within one timestamp of the ROHD simulator. This scenario probably already happens, but it would be good...

There's already support for accessing registered ports of `ExternalSystemVerilogModule`s, but it would be cool to be able to access other non-port signals in modules or submodules in the SystemVerilog. This...

A bug exists in ROHD related to clock dividers: https://github.com/intel/rohd/issues/191 The logic in cosimulation is similar to the logic of sequential logic in a plain ROHD simulation. We should review...

Some listeners and subscriptions from `Cosim.connectCosimulation` do not cancel when a simulation ends. This means if the simulation is reset and started again, at least there's a performance penalty and...

There's already arguments available for compile, "extra", filelists, etc. but there are others not supported in `Cosim` `Module`s. A couple major ones are simulation args and plusargs. The cocotb docs...

It can be tedious to build a cosim wrapper for a SystemVerilog module for cosimulation. Since enough information is provided anyways to build and simulate the module, it would be...

There is some limited typing of cosim messages in both the Dart and Python sides of the package. Creating some better types for different types of messages could make the...

### Describe the bug For example, when shifting by an integer (e.g. `