Max Korbel

This is a good opportunity to add a microbenchmark

@chykon thank you for the note! I'm actually out of town at the moment so my time is unusually restricted. We really appreciate the feedback and welcome suggestions and ideas!...

It might be a good idea to make a new custom module so that the generated output SystemVerilog has `[]` instead of `

Thank you for reporting this! I was able to reproduce the issue and I'm looking into a root-cause and fix.

I found a bug in the logic which collapses assignments of constants in generated SystemVerilog in certain scenarios, which when fixed makes your code example pass. I added a test...

Regarding the in-lining of constants and readability, it can be a matter of preference and style and it is difficult to judge algorithmically which scenarios may look more appealing and...

I'm able to reproduce a failure in your example code, but I'm still trying to figure out what the failure means since I'm not that familiar with the details of...

Thank you for the shortened example, it's very helpful towards debugging this!

I think I've root caused a collection of issues in `Combinational` sensitivity lists that causes the behavior you're seeing, as well as some unexpected intermediate signal contention and incomplete `swizzle`...

I've created a PR that should fix this issue: https://github.com/intel/rohd/pull/166 You can try it out and let me know if you see any issues still. I plan to merge it...