Max Korbel comments

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                                            Max Korbel

Fixed point support

Thanks for the context, very helpful! I think this sounds quite achievable.

Write part-assign automation for `LogicArray`s

Closed in #456

Add helper function(s) to "split" `Logic`s and `LogicValue`s

This is already implemented in `Logic` via `elements`, but still needs something similar added for `LogicValue`

Improving the `StateMachine` view in `vcd`

Great suggestion. I think something similar might be nice for `Pipeline` as well. As a note, it will require a little overhead in the implementation to properly generate inputs and...

Allow graceful error handling in `Simulator.throwException`

Additionally, if anything catches the `Simulator`'s exceptions, the `Simulation.simulationEnded` never completes, which also means that any `Simulator.reset()` will never complete!

The order in which `clock` is connected to module inputs affects how the circuit behaves

Thank you for providing the detail and something to reproduce this. I haven't started debugging yet but from your description it does sound like a bug.

Specifying the Sequential vs. Combinational driving of logic in `FiniteStateMachine`

Good point, thanks for the suggestion!

Add automation for code coverage in PRs and pushes

> Can I take it? Sure, it's all yours, thanks! > Are there any deadlines? Nope, no firm deadline :)

Add the ability to configure WaveDumper to ignore internal signals

This is a great suggestion, thanks! It could really save a lot of performance on wave dumping, as well.

Rewrite comments on `example/tree.dart`

Good points, thank you for filing!