Tim 'mithro' Ansell

@kgugala

@hzeller had ideas. I think he has doing this for https://github.com/zachjs/sv2v/pull/38

The hacker and pvt devices have different pin out configurations and a few other small changes.

See the schematic link from https://workshop.fomu.im/en/latest/requirements.html#required-hardware

See https://github.com/f4pga/prjuray - https://github.com/SymbiFlow/f4pga-arch-defs/pull/1651 GitHubGitHub - f4pga/prjuray: Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format. - GitHub...

Support for Ultrascale and Ultrascale+ will most likely end up happening through the FPGA Interchange Format rather than this architecture definitions approach. You can see some initial xczu7ev support in...

I would suggest that the; * `Resource` object have an optional attribute called `silkscreen_reference` which takes an arbitrary string. * `Resource` objects have an optional attribute called `location_information` which takes...

Was thinking something like `add_constant` ```python class BaseSoC(SoCSDRAM): def __init__(self, platform, **kwargs): self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) ```

Provides a define in the C header file. CSRConstant could be another option. Or you could write out a CSV or other configuration file?

I agree that the output side probably doesn't make sense in nMigen's core -- was just trying to provide some type of example of how it might end up getting...