Tim 'mithro' Ansell comments

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                                            Tim 'mithro' Ansell

gtp: add full LiteSATA example with workarounds

Seems like there are some generic improvements to the LiteX output that are mixed in with the GTP/libsata addition?

Covering more topics

@vshymanskyy Any chance you would be able to send us some pull requests? We would gladly merge them. The new sphinx version of the workshop makes it easier to include...

Wrong synthesis result when `signed` signal is used for bit indexing

At a high level -- if the result works in Vivado, then it should probably also work in SymbiFlow. If Vivado's behaviour is different to the standard then we might...

Add a nmigen example

@cr1901 @RobertBaruch @whitequark - Any chance you would be interested in adding some stuff here? Happy to send you some Fomu hardware.

Add translation support for case.

You might want to checkout what nmigen did. Sorry on my phone otherwise would provide a direct link.

Import background information about FPGA toolchains from SymbiFlow docs

This is actually one of the reasons I converted to using Sphinx for the workshop.

Import background information about FPGA toolchains from SymbiFlow docs

@mgielda

Misunderstanding on Migen and LiteX page

I don't think #110 fixes this. It still isn't clear that the code should be added before the builder and there is no error if you try to add something...

Delete utils/vpr_fixup_post_synth.py

FYI - @kgugala

Add Verilator in multiple modes

#506 is related