Tim 'mithro' Ansell comments

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                                            Tim 'mithro' Ansell

Got this error while running symbolator on a verilog file

We are mainly using symbolator with verilog and don't have a huge interest in VHDL (but perfectly happy for other people to work on that).

Got this error while running symbolator on a verilog file

@sumanth-kalluri - Don't have any plans to dramatically improve things in symbolator, we just need basic block diagrams for things like the skywater-pdk. There are other projects working on the...

Got this error while running symbolator on a verilog file

I think supporting Python 3 is important.

Got this error while running symbolator on a verilog file

@sumanth-kalluri -- There was also a discussion about this topic at https://groups.google.com/forum/#!msg/eda-playground/Mh9bOhC7FNQ/w7GKEEqlAAAJ and potential of using Surelog to do this -> https://github.com/alainmarcel/Surelog

Create Index of Verilog Simulation Models

Any idea why CI is failing?

Create Index of Verilog Simulation Models

@rw1nkler -- Can you rebase this -- I think it is mostly ready to merge?

USB-to-UART core desirable

This is currently desired and @tcal-x was looking into doing this [with LUNA](https://luna.readthedocs.io/en/latest/custom_hardware.html#full-speed-using-fpga-i-o) recently if I understand correctly. The goal here is to enable people to use the Fomu in...

Tim 'mithro' Ansell

Got this error while running symbolator on a verilog file

Got this error while running symbolator on a verilog file

Got this error while running symbolator on a verilog file

Got this error while running symbolator on a verilog file

Create Index of Verilog Simulation Models

Create Index of Verilog Simulation Models

USB-to-UART core desirable

USB-to-UART core desirable

WIP - Tool for generating stuff related to latches

gtp: add full LiteSATA example with workarounds