Tim 'mithro' Ansell comments

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                                            Tim 'mithro' Ansell

Added a section on channel wire modeling.

I'm the wrong person to ask here. @mkurc-ant / @acomodi / @kgugala - Could you review and see if this makes sense? @gatecat might be able to provide some thoughts...

Some basejump_stl files are abstract base classes and should be marked parse only

FYI - @taylor-bsg

Some basejump_stl files are abstract base classes and should be marked parse only

@taylor-bsg - I can't find this magical bsg_micro repository?

Some basejump_stl files are abstract base classes and should be marked parse only

@taylor-bsg - Why do you have @bsg-idea and @bespoke-silicon-group!?

Some basejump_stl files are abstract base classes and should be marked parse only

@taylor-bsg - You must have a source repo for the stuff before it goes through sv2v right?

Problems When Module Parameters are Passed Single Words of a Multi Bit Array in SystemVerilog but not Verilog

@kgugala - You were talking about this recently IIRC?

Specification of language standard

@Nic30 We should probably tag them with the correct standard version?

Add a rust section to the CPU bit

@tiwalun just promised to add a blink example. I'm waiting on him to do it now :-)

This adds a BASIC touch support to the verilog blink example

@LeonFedotov This looks good - did you mean to close it?

This adds a BASIC touch support to the verilog blink example

@LeonFedotov -- if you want extra Fomus, I'm happy to give you some for doing this...