Supporting Ultrascale+ is in plan?

[the-centry]

If there is a plan to support u+ device? Thanks so much!

[mithro]

See https://github.com/f4pga/prjuray - https://github.com/SymbiFlow/f4pga-arch-defs/pull/1651

GitHub

GitHub - f4pga/prjuray: Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format. - GitHub - f4pga/prjuray: Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bi...

[mithro]

Support for Ultrascale and Ultrascale+ will most likely end up happening through the FPGA Interchange Format rather than this architecture definitions approach.

You can see some initial xczu7ev support in that method -> https://chipsalliance.github.io/fpga-interchange-tests/#xczu7ev

FPGA interchange tests — fpga-interchange-tests 0.1 documentation

[the-centry]

Support for Ultrascale and Ultrascale+ will most likely end up happening through the FPGA Interchange Format rather than this architecture definitions approach.

You can see some initial xczu7ev support in that method -> https://chipsalliance.github.io/fpga-interchange-tests/#xczu7ev

FPGA interchange tests — fpga-interchange-tests 0.1 documentation

Ok,thanks so much! This project fpga-interchange seems like that next-pnr generate *bba through rapidwright,and the use next-pnr place and route! It may meet problem while device's data over the limit of capnp! It means that the work generating vpr's device data through rapidwright for Ultrascale+ is in plan?

FPGA interchange tests — fpga-interchange-tests 0.1 documentation