circt
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Circuit IR Compilers and Tools
This commit adds the basic configuration files needed for a VS Code extension that provides Verilog language server protocol (LSP) support through CIRCT. While it may seem unusual to include...
@seldridge did some digging: The issue appears to be that we have an i8 attribute and it is being converted to an APSInt: ``` [firtool] Running "firrtl-imconstprop" Assertion failed: (!getType().isSignlessInteger()...
If `CIRCT_INCLUDE_TESTS=OFF` but this source file is compiled (only to eventually be DCEd) `circt::python::populateDialectRTGTestSubmodule` is malformed. With explicit `namespace circt::python` it works both ways.
If I'm reading this right, there could be a set of comb canonicalizers doing the following simplification from ```mlir hw.module @alias(in %init : i4, in %in0 : i1, in %in1...
When I manually cancelled CI run it saved incomplete cache (See https://github.com/llvm/circt/actions/runs/13425801396/job/37508404535). Subsequent PRs use the incomplete cache which requires full build of LLVM. Cache should be saved when it's...
Please check this PR(https://github.com/llvm/circt/pull/8210/files) to view the details. Or for example: ``` moore.module @crash(in %in0: !moore.i32, in %in1: !moore.i32) { %var = moore.variable : moore.procedure always_comb { %0 = moore.pows...
Arcilator is currently very easy to break if a public module is instantiated anywhere. In that case the module hierarchy does not get flattened completely, but the public module remains...
Hi, I think I might have encountered a bug in the Verilog frontend of CIRCT. Below is the Verilog code in `bug.v`: ```verilog module Bug (O, A, B, C); input...
