circt
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llvm
Circuit IR Compilers and Tools
```firrtl FIRRTL version 4.0.0 circuit Foo: %[[ {"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Foo>r"} ]] public module Foo: input c : Clock input i : UInt input r : AsyncReset output o : UInt inst...
Script which, using a best-effort attempt to find or grab a vcpkg installation, installs grpc (+protobuf and zlib). Required for the ESI runtime.
The type of reset inferred for a module port changes the implementation of any register which uses it. Since extmodules are separately compiled modules from other circuits, it does not...
There is some logic when wiring the annotated reset to target registers, that we try to find a location to create a reset wire which dominates all use-sites. The problem...
The FullAsynchronousResetTransform no longer removes its annotation, which can lead to problems where the pass is no longer idempotent. It seems like some work has gone in to minimizing the...
Given this FIRRTL: ```firrtl FIRRTL version 4.0.0 circuit Foo: %[[ {"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Foo>r"} ]] public module Foo: input p : UInt input r : AsyncReset input c : Clock inst bar...
The InferResetsPass implements what is logically two separate passes, and it would be cleaner to make that distinction concrete.
Given: ```firrtl FIRRTL version 3.0.0 circuit Foo: module Foo: input clock : Clock reg r : Reset, clock module Bar: input in: {reset: Reset} ``` Running it through `firtool` with...
Given: ```fir FIRRTL version 3.0.0 circuit Foo: %[[ {"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Foo>reset"} ]] module Foo: input p : UInt input r : AsyncReset when p: wire reset : AsyncReset inst bar of...
This forces dialects to handle storing their own types in their own ops and not tie them to firrtl connect semantics. To make this a bit easier, a new connect-like...
