[FIRRTL] FART: Should not modify public module ports

[youngar]

FIRRTL version 4.0.0
circuit Foo: %[[
  {"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Foo>r"}
]]
  public module Foo:
    input c : Clock
    input i : UInt<8>
    input r : AsyncReset
    output o : UInt<8>

    inst bar of Bar
    connect bar.c, c
    connect bar.i, i
    connect o, bar.o

  public module Bar:
    input c : Clock
    input i : UInt<8>
    output o : UInt<8>
    reg r : UInt<8>, c
    connect r, i
    connect o, r

through firtool yields:

module Bar(
  input        r,
               c,
  input  [7:0] i,
  output [7:0] o
);

We have modified the ports of Bar by adding r, changing its public interface. I expect that boring the reset signal would not modify the public module interface, but I do not know exactly what should happen. Possibly we cut the reset domain boundary at public modules, or maybe we clone Bar into a private module with the added port, and instantiate that instead under Foo.