[FIRRTL] InferResets: does not catch uninferred abstract resets

[youngar]

Given:

FIRRTL version 3.0.0
circuit Foo:
  module Foo:
    input clock : Clock
    reg r : Reset, clock

  module Bar:
    input in: {reset: Reset}

Running it through firtool with no additional options, produces verilog. This should be an error as there are two uninferred abstract resets in this design. The first problem is that we are not checking module bodies for uninferred resets. The second problem is that when checking ports for uninferred resets we do not handle aggregates.

You can see that InferResets leaves behind the abstract resets:

firrtl.circuit "Foo" {
  firrtl.module @Foo(in %clock: !firrtl.clock) attributes {convention = #firrtl<convention scalarized>} {
    %r = firrtl.reg %clock : !firrtl.clock, !firrtl.reset
  }
  firrtl.module private @Bar(in %in: !firrtl.bundle<reset: reset>) {
  }
}

// -----// IR Dump After InferResets (firrtl-infer-resets) //----- //
firrtl.circuit "Foo" {
  firrtl.module @Foo(in %clock: !firrtl.clock) attributes {convention = #firrtl<convention scalarized>} {
    %r = firrtl.reg %clock : !firrtl.clock, !firrtl.reset
  }
  firrtl.module private @Bar(in %in: !firrtl.bundle<reset: reset>) {
  }
}