circt
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Circuit IR Compilers and Tools
This PR replaces the "HWToSV" conversion pass with the functionally identical "ProceduralCoreToSV". For the moment, it only converts the `hw.triggered` operation to `sv.always`. The motivation for this change is to...
Input: ``` FIRRTL version 4.0.0 circuit Foo: option Platform: FPGA ASIC module DefaultTarget: input clock: Clock module FPGATarget: input clock: Clock module ASICTarget: input clock: Clock public module Foo: input...
I came across the following crash when running some experiments: ``` firrtl FIRRTL version 4.0.0 circuit Foo: %[[ { "class": "sifive.enterprise.firrtl.TestBenchDirAnnotation", "target": "verification" } ]] public module Foo: input a:...
We worked around an issue originally in #7102 and again in #7328. From @dtzSiFive: > Doing this lazily is nice, although perhaps as we lean more on these things we're...
`moore.*assign` has a new extra operand--`enable` to capture the if condition, like `moore.assign %dst, %src if %enable` `PullNonBlockingUp` pass is aimed at pulling non-blokcing assignments upwards. From: ``` moore.procedure {...
This pass is used to merge `moore.extract_ref` together in the big-endian order without existing in `if/for` statements and nested `moore.extract_ref`. For example: ``` bit [31:0] arr; assign arr[23:16] = 8'd5;...
On the bottom of https://circt.llvm.org/ it says "Nightly performance plots: https://circt.org/perf/" but this does not work. Given that the main page is at https://circt.llvm.org/ I tried https://circt.llvm.org/perf/ but that is...
As in title - the main link to the right is broken, it should be https://circt.llvm.org/ Probably easy to fix but you need admin rights for it :)
TBD Just testing this against the CI for the moment.
Generated ram blocks have an output assignment which assigns the read port value to X when read is not enabled. This can cause problems with some design flows or tools....
