circt

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Emitted SV uses variable before declaration

1

Consider: ```mlir hw.module @hoist_reg(in %dummy : i32, in %dummy2 : i32, out out : i17) { %res_reg = sv.reg : !hw.inout sv.initial { %tmp = sv.reg init %dummy : !hw.inout...

dtzSiFive

As of today, it is impossible to use the pycde API in a way which pleases python type checkers (e.g. mypy). Make this possible. Will require API changes. Not sure...

teqdruid

Text MLIR represetation is used when custom bytecode encoding are not defined. It would be good to add foundamental types/attributes frequently used in HW

uenoku

[Scheduling] Logging via the containing op can be too verbose

1

@7FM noted: > I find the logging sometimes a bit too verbose, especially when the `containingOp` is very large. A hacky workaround that I sometimes use OoT is something like...

jopperm

This patch lowers `memref::GetGlobalOp` and write data that it carries to corresponding json files, so that they can be used later by Calyx. Json data will be written to the...

jiahanxie353

[SCFToCalyx] Add support for sequential read MemRefType memories

8

If a FuncOp argument is of `MemRefType` and has the boolean attribute `calyx.sequential_reads` set to true, consider the read accesses to that memory as sequential, which adds a "read_en" signal...

xerpi

Consider this input: ``` firrtl.circuit "MatchTest" { firrtl.module @MatchTest(in %i: !firrtl.enum) attributes {convention = #firrtl} { %c0_ui8 = firrtl.constant 0 : !firrtl.const.uint %0 = firrtl.enumcreate Some(%c0_ui8) : (!firrtl.const.uint) -> !firrtl.enum...

dtzSiFive

Consider: ``` firrtl.circuit "MatchInline" { firrtl.module @MatchInline(in %i: !firrtl.enum, out %o: !firrtl.uint) attributes {convention = #firrtl} { %c255_ui8 = firrtl.constant 255 : !firrtl.uint {name = "c_out"} %c0_ui8 = firrtl.constant 0...

dtzSiFive

Can offload loops with simple memory access to FPGA/GPU? If request for offload (such as `#pragma`), give compiler errors (such as `static_assert` does) if the loops use memory access patterns which can not map to GPUs?

3

... (or, if can not output a loop to GPU, just fall back to CPU.) https://tilera.github.io/llvm/ can output to 64/72 core Tilera ([_TILE-Gx_](https://wikipedia.org/wiki/TILE-Gx)) CPUs. Most GPUs now have [_GPGPU_](https://wikipedia.org/wiki/GPGPU) memory...

SwuduSusuwu

```bash $ circt-opt test/Conversion/ExportVerilog/hw-dialect.mlir --test-apply-lowering-options='options=emittedLineLength=100,emitBindComments' -export-verilog -verify-diagnostics -o a.mlir $ circt-opt a.mlir a.mlir:788:56: error: expected non-function type %1 = sv.wire {hw.verilogName = "_GEN"} : !hw.inout ```

uenoku