circt
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llvm
Circuit IR Compilers and Tools
Caught a small issue with flattening the load. Say we have an example: ```mlir module { func.func @main(%arg0: memref) { %c1 = arith.constant 1 : index %c2 = arith.constant 2...
The following SV currently crashes because `x` is lowered to an `i32`, which is unassignable, instead of a `ref`, which would be assignable: ``` function void foo(int x); x =...
Previously: #7467. ```mlir firrtl.circuit "LayersProbe" { firrtl.layer @A bind {} firrtl.module @LayersProbe(out %o: !firrtl.bundle) { firrtl.layerblock @A { %0 = firrtl.ref.send %o : !firrtl.bundle } } } ``` `circt-opt --firrtl-lower-layers...
Currently, there is (at least one) error upon which export verilog reports the error to the output but does not fail: `op emission to Verilog not supported`. This behavior may...
Current testing infrastructure in CIRCT makes it inconvenient to express test intent in the IR, these thus often rely on external tools and/or libraries implemented in the front-end languages to...
A `firrtl.layerblock` is supposed to contain no operations which write outside the `layerblock`. Improve the verifier for the `layerblock` to be able to check this. The problem is specifically with...
inlineInstances/flattenInstances: * Walk entire body, not only top-level operations. Fixes missing instances and allows inlining them when conservatively legal. * Reject inlining instances under when/match. inlineInto/flattenInto: Walk entire body using...
sv: ```sv import "DPI-C" function void dpi(input int a []); module DPI( ); wire [31:0] _GEN_0 [2:0]; // this style is currently emitted by ExportVerilog int _GEN_1 [2:0]; assign _GEN_0...
Input: ```firrtl FIRRTL version 4.0.0 circuit ConstFlip : extmodule Sink : input x : const UInt public module ConstFlip : output out : { x : const { flip y...
When an `AcceleratorConnection` is torn down and destructed, accesses to its associated `Accelerator`s and their associated ports will be memory violations. This is (fairly) well documented in the API, but...