[FIRRTL][LowerLayers] ref.send capture of non-passive doesn't work

[dtzSiFive]

Previously: #7467.

firrtl.circuit "LayersProbe" {
  firrtl.layer @A bind {}
  firrtl.module @LayersProbe(out %o: !firrtl.bundle<x flip: uint<1>>) {
    firrtl.layerblock @A {
      %0 = firrtl.ref.send %o : !firrtl.bundle<x flip: uint<1>>
    }
  }
}

circt-opt --firrtl-lower-layers --no-implicit-module --mlir-print-ir-after-failure yields:

<stdin>:5:12: error: 'firrtl.matchingconnect' op operand #0 must be a sized passive base type (contains no uninferred widths, or flips) or foreign type, but got '!firrtl.bundle<x flip: uint<1>>'
      %0 = firrtl.ref.send %o : !firrtl.bundle<x flip: uint<1>>
           ^
<stdin>:5:12: note: see current operation: "firrtl.matchingconnect"(%0, %arg0) : (!firrtl.bundle<x flip: uint<1>>, !firrtl.bundle<x flip: uint<1>>) -> ()
// -----// IR Dump After LowerLayers Failed (firrtl-lower-layers) //----- //
#loc = loc("<stdin>":5:12)
#loc1 = loc("<stdin>":3:34)
"firrtl.circuit"() ({
  "sv.verbatim"() {format_string = "`ifndef layers_LayersProbe_A\0A`define layers_LayersProbe_A", output_file = #hw.output_file<"layers_LayersProbe_A.sv", excludeFromFileList>, symbols = []} : () -> ()
  "firrtl.module"() ({
  ^bb0(%arg1: !firrtl.bundle<x flip: uint<1>>):
    %1 = "firrtl.ref.send"(%arg1) : (!firrtl.bundle<x flip: uint<1>>) -> !firrtl.probe<bundle<x: uint<1>>>
  }) {annotations = [], convention = #firrtl<convention internal>, layers = [], portAnnotations = [], portDirections = array<i1: false>, portLocations = [#loc], portNames = ["o"], portSyms = [], portTypes = [!firrtl.bundle<x flip: uint<1>>], sym_name = "LayersProbe_A", sym_visibility = "private"} : () -> ()
  "firrtl.module"() ({
  ^bb0(%arg0: !firrtl.bundle<x flip: uint<1>>):
    %0 = "firrtl.instance"() {annotations = [], layers = [], lowerToBind, moduleName = @LayersProbe_A, name = "a", nameKind = #firrtl<name_kind droppable_name>, output_file = #hw.output_file<"layers_LayersProbe_A.sv", excludeFromFileList>, portAnnotations = [[]], portDirections = array<i1: false>, portNames = ["o"]} : () -> !firrtl.bundle<x flip: uint<1>>
    "firrtl.matchingconnect"(%0, %arg0) : (!firrtl.bundle<x flip: uint<1>>, !firrtl.bundle<x flip: uint<1>>) -> ()
  }) {annotations = [], convention = #firrtl<convention internal>, layers = [], parameters = [], portAnnotations = [], portDirections = array<i1: true>, portLocations = [#loc1], portNames = ["o"], portSyms = [], portTypes = [!firrtl.bundle<x flip: uint<1>>], sym_name = "LayersProbe"} : () -> ()
  "sv.verbatim"() {format_string = "`endif // layers_LayersProbe_A", output_file = #hw.output_file<"layers_LayersProbe_A.sv", excludeFromFileList>, symbols = []} : () -> ()
}) {annotations = [], name = "LayersProbe"} : () -> ()