[ExportVerilog] Pass should fail if any failure occurs while running

[teqdruid]

Currently, there is (at least one) error upon which export verilog reports the error to the output but does not fail: op emission to Verilog not supported. This behavior may have been desirable during the development of the pass, but now creates problems -- not the least of which is some of our tests passing spuriously (#7414 and maybe #4770).

It's well past time to change this behavior.

[teqdruid]

@darthscsi @seldridge WDYT?

[seldridge]

Agree. Hard error.

[dtzSiFive]

Agree!!