[FIRRTL][LowerSignatures] Const is dropped, breaking IR

[dtzSiFive]

Input:

FIRRTL version 4.0.0

circuit ConstFlip :
  extmodule Sink :
    input x : const UInt<1>
  public module ConstFlip :
    output out : { x : const { flip y : UInt<1> } }

    inst s of Sink
    connect s.x, out.x.y

firtool --mlir-print-ir-after-failure produces:

const-flip.fir:6:10: error: type mismatch between destination '!firrtl.const.uint<1>' and source '!firrtl.uint<1>'
  public module ConstFlip :
         ^
const-flip.fir:6:10: note: see current operation: "firrtl.connect"(%2, %arg0) : (!firrtl.const.uint<1>, !firrtl.uint<1>) -> ()
// -----// IR Dump After LowerSignatures Failed (firrtl-lower-signatures) //----- //
"firrtl.circuit"() ({
  "firrtl.extmodule"() ({
  }) {annotations = [], convention = #firrtl<convention scalarized>, layers = [], parameters = [], portAnnotations = [[]], portDirections = array<i1: false>, portLocations = [loc("const-flip.fir":5:11)], portNames = ["x"], portSyms = [], portTypes = [!firrtl.const.uint<1>], sym_name = "Sink", sym_visibility = "private"} : () -> ()
  "firrtl.module"() ({
  ^bb0(%arg0: !firrtl.uint<1>):
    %0 = "firrtl.wire"() {annotations = [], name = "out", nameKind = #firrtl<name_kind interesting_name>} : () -> !firrtl.bundle<x: const.bundle<y flip: uint<1>>>
    %1 = "firrtl.subfield"(%0) {fieldIndex = 0 : i32} : (!firrtl.bundle<x: const.bundle<y flip: uint<1>>>) -> !firrtl.const.bundle<y flip: uint<1>>
    %2 = "firrtl.subfield"(%1) {fieldIndex = 0 : i32} : (!firrtl.const.bundle<y flip: uint<1>>) -> !firrtl.const.uint<1>
    "firrtl.connect"(%2, %arg0) : (!firrtl.const.uint<1>, !firrtl.uint<1>) -> ()
    %3 = "firrtl.subfield"(%0) {fieldIndex = 0 : i32} : (!firrtl.bundle<x: const.bundle<y flip: uint<1>>>) -> !firrtl.const.bundle<y flip: uint<1>>
    %4 = "firrtl.subfield"(%3) {fieldIndex = 0 : i32} : (!firrtl.const.bundle<y flip: uint<1>>) -> !firrtl.const.uint<1>
    %5 = "firrtl.instance"() {annotations = [], layers = [], moduleName = @Sink, name = "s", nameKind = #firrtl<name_kind interesting_name>, portAnnotations = [[]], portDirections = array<i1: false>, portNames = ["x"]} : () -> !firrtl.const.uint<1>
    "firrtl.matchingconnect"(%5, %4) : (!firrtl.const.uint<1>, !firrtl.const.uint<1>) -> ()
  }) {annotations = [], convention = #firrtl<convention scalarized>, layers = [], portAnnotations = [[]], portDirections = array<i1: false>, portLocations = [loc("const-flip.fir":7:12)], portNames = ["out_x_y"], portSyms = [], portTypes = [!firrtl.uint<1>], sym_name = "ConstFlip"} : () -> ()
}) {annotations = [], name = "ConstFlip"} : () -> ()

[dtzSiFive]

LowerTypes also has the same bug. firtool --parse-only|circt-opt --firrtl-lower-types --mlir-print-ir-after-failure:

<stdin>:8:7: error: 'firrtl.matchingconnect' op failed to verify that operands must be structurally equivalent
      firrtl.matchingconnect %s_x, %1 : !firrtl.const.uint<1>
      ^
<stdin>:8:7: note: see current operation: "firrtl.matchingconnect"(%0, %arg0) : (!firrtl.const.uint<1>, !firrtl.uint<1>) -> ()
// -----// IR Dump After LowerFIRRTLTypes Failed (firrtl-lower-types) //----- //
"firrtl.circuit"() ({
  "firrtl.extmodule"() ({
  }) {annotations = [], convention = #firrtl<convention scalarized>, layers = [], parameters = [], portAnnotations = [[]], portDirections = array<i1: false>, portLocations = [loc("<stdin>":3:39)], portNames = ["x"], portSyms = [], portTypes = [!firrtl.const.uint<1>], sym_name = "Sink", sym_visibility = "private"} : () -> ()
  "firrtl.module"() ({
  ^bb0(%arg0: !firrtl.uint<1>):
    %0 = "firrtl.instance"() {annotations = [], layers = [], moduleName = @Sink, name = "s", nameKind = #firrtl<name_kind interesting_name>, portAnnotations = [[]], portDirections = array<i1: false>, portNames = ["x"]} : () -> !firrtl.const.uint<1>
    "firrtl.matchingconnect"(%0, %arg0) : (!firrtl.const.uint<1>, !firrtl.uint<1>) -> ()
  }) {annotations = [], convention = #firrtl<convention scalarized>, layers = [], parameters = [], portAnnotations = [[]], portDirections = array<i1: false>, portLocations = [loc("<stdin>":4:34)], portNames = ["out_x_y"], portSyms = [], portTypes = [!firrtl.uint<1>], sym_name = "ConstFlip"} : () -> ()
}) {annotations = [], name = "ConstFlip"} : () -> ()