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Circuit IR Compilers and Tools
Parsing a negative preset value for the `FirRegOp` will currently produce the slightly inappropriate message "preset value too large". On the other hand, the printer does output negative integers if...
Chisel provides a **unsafe** version of get class type: `Class.unsafeGetClassTypeByName`, this is used when user need a Class Type w/o get the Scala val of which. This will cause an...
This commit updates the heuristic to infer the enable signal drivers. Since temporary wires can be introduced by circt passes, the immediate `getConnectSrc` is not enough to infer the enable...
Passes
I am just starting out with CIRCT I wanted to know the procedure on lowering dialects to Verilog. I went through the CIRCT documentation and came upon passes. I want...
Add support for `verif.assert` and `sv.assert.concurrent` operations to the Arc dialect and passes. When lowering towards LLVM, the asserts should lower to an `scf.if` operation that checks whether their condition...
Handle the `RWProbeOp` in `CheckCombLoop`. This fixes https://github.com/llvm/circt/issues/6820
Example FIRRTL: ``` FIRRTL version 3.3.0 circuit Bar : module Foo : input clock : Clock output clockProbe_bore : RWProbe define clockProbe_bore = rwprobe(clock) module Bar : input clock :...
In https://github.com/llvm/circt/pull/6811, we relaxed the owning module constraint for local targets. This should be safe, but is generally not something we want to do. The problem is we have local...
A useful thing to lint is to check that there are no cross module references inside design code. (Note: it is not well defined what is "design code" vs. what...
In https://github.com/llvm/circt/issues/6793, we faced an issue where newly added asserts in DialectConversion were triggered by uses of rewriter.replaceAllUsesWith. This is because RewriterBase::replaceAllUsesWith is not currently supported by DialectConversion. To work...