circt
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Circuit IR Compilers and Tools
The FIRRTL spec changes to making commas mandatory. Previously, these were whitespace. While no changes are necessary to the FIRRTL parser in CIRCT (as it currently treats commas as whitespace...
As suggested in a discussion in PR #6773, consider turning the AST visitors in ImportVerilog into a non-recursive, worklist-based implementation.
If the register has a const reset value, we can replace but we cannot replace it with a non-constant reset value.
## Please just view the `MooreOps.cpp` file to check the related implementation. ### First ``` module Foo; int x, y; always_comb begin int a; a = x + 1; y...
This PR stacks on #6952 and is the first part of #6953 , in which I was asked to break down to smaller patches. This PR adds support to the...
Some simulators like Verilator have very poor support for SVA syntax and will sometimes give a false positives when they are used. This PR adds an option that allows for...
Create a new op `NamedConstantOp` for three elaboration-time constants: `parameter`, `localparam`, and `specparam`, which distinguishes 'parameter' from constants and variables.
Translate union type only from slang to moore. Add moore.union_create and morre.union_extract OPs. More tests and Mem2Reg pass will be imporved.
`moore.net` is not considered for the time being. And just lower the variables of two-state and four-state(have initial value) into `hw.wire`. If the variables don't have an initial value, assign...
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