Jim Huang
Jim Huang
To achieve the goal of integrating a portable JIT compiler (#81) , we plan to implement a multi-tier compilation framework. We will start with the Fast JIT tier and then...
The JALR (Jump and Link Register) instruction updates the program counter to a target address by adding a sign-extended 12-bit immediate to the value of the rs1 register and saves...
[TLSF](http://www.gii.upv.es/tlsf/) (Two-Level Segregated Fit) dynamic memory allocation algorithm is guaranteed to complete allocation and deallocation operations in constant time, suitable for real-time applications. Reference: * [Benchmarking Malloc with Doom 3](https://www.forrestthewoods.com/blog/benchmarking-malloc-with-doom3/)...
The prototype of the fast tier-1 JIT compiler (#283) introduces an advanced sampling-based profiler and a tier-up optimization strategy. The two fundamental components for this are: 1) a multi-tiered recompilation...
Function `muldivmod` in `src/jit_x64.c ` is incomplete: ```c /* Short circuit for imm == 0 */ if (!reg && imm == 0) { assert(NULL); if (div || mul) { /*...
A block replacement algorithm continues to receive attention for the improvement of its hit ratio. Numerous replacement algorithms have been proposed, among which LIRS stands out with its consistently higher...
[rv8](https://github.com/michaeljclark/rv8) demonstrates how RISC-V instruction emulation can benefit from JIT compilation and aggressive optimizations. However, it is dedicated to x86-64 and hard to support other host architectures, such as Apple...
Superinstructions are well-known techniques for improving the performance of interpreters. Superinstructions eliminate jumps between VM operations (interpreter dispatch) and enable more optimizations in the merged code. Adopting an approach to...
[libriscv](https://github.com/libriscv/libriscv) is a compact yet comprehensive RISC-V userspace emulator library crafted for effortless embedding and extensive adaptability. It boasts a high-performing interpreter and an experimental binary translator, driven by [TinyCC](https://github.com/TinyCC/tinycc)....
Although there have been improvements in the performance of RISC-V instruction interpretation, the reasons why wasm3 outperforms in certain performance metrics, such as CoreMark, remain unclear. Tested on AMD Ryzen...