Jim Huang
Jim Huang
Since AMaCC was influenced by [c4](https://github.com/rswier/c4) design, it assumed 32-bit target. However, it is confusing while 64-bit targets are considered. There were preliminary patches for proposed portability changes: * [Making...
[9cc](https://github.com/rui314/9cc) is a successor of 8cc, 9cc can be understood extremely easily while creating a compiler that generates reasonably efficient assembly. Will 9cc be modified to generate elvm IR?
On `develop` branch, the program `benchmarks` fails to run resulting from optimizations done by `gcc` with `O3`: ``` -- no-op limit 1000000 -- wall 1.033 clock 2.999 => 968493.0 /...
[Apache Impala](https://impala.apache.org/) adopts SSE2NEON along with partial SSE4.2 text processing intrinsics support in file [be/src/util/sse-util.h](https://github.com/apache/impala/blob/master/be/src/util/sse-util.h): * `cmpestrm` * `cmpestri` However, the above were neither optimized nor generic. Instead, we can...
The project has several reference hyperlinks to Microsoft website. Due to [Microsoft Product Lifecycle](https://support.microsoft.com/en-us/lifecycle/selectindex), however, the content of MSDN is no longer updated regularly. We shall migrate to [Intel Intrinsics...
Quote from Jukka Liimatta > _mm_popcnt_* uses store, when vget_lane_* would probably be a better fit.. the compiler will optimize the store into lane extract more likely but now it...
`sse2neon` aims to support SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AES extension, and AVX intrinsics would be excluded. @danlark1 pointed out: > Technically speaking, `_mm_fmadd_ps` is not an SSE...
Quote from top-level documentation: > Benchmark > `~/lwan/build$ make benchmark` > This will compile `testrunner` and execute benchmark script `src/scripts/benchmark.py`. However, after configuring cmake, I found no target named `benchmark`.
Both `src/arm-codegen` and `src/riscv-codegen.c` have some functions in common. The code generation can be refactored with the following changes: 1. split the shared functions/variables to new file `src/codegen.c` from src/{arm,riscv}-codegen.c...
Some Arm targets such as Cortex-A9 might lack of integer division instructions, and the current `shecc` would not generate the correct instruction sequence for them. Consequently, we have to provide...