Jim Huang

Implement performance counters and timers

3

RISC-V ISAs provide a set of up to 32×64-bit performance counters and timers. RV32I provides a number of 64-bit read-only user-level counters, which are mapped into the 12-bit CSR address...

Run `riscv-arch-test` in CI pipeline

1

The build system is capable of running the tests for specific extensions, such as I, M, C, Zifencei, privilege, and F. However, there is no regular validation for each pull...

Integrate `embench-iot` for benchmarking

2

[Embench benchmark suite](https://github.com/embench/embench-iot) is designed to test the performance of deeply embedded systems. - The measurement of execution performance is designed to use "hot" caches. Thus each benchmark executes its...

There are various combinations of build-time configurations, such as * (`ENABLE_RV32C` = 0) AND (`ENABLE_COMPUTED_GOTO` = 0) * (`ENABLE_RV32C` = 1) AND (`ENABLE_COMPUTED_GOTO` = 0) * (`ENABLE_SDL` = 0) AND...

Run modified xv6 for RV32I

1

Recently, [MIT xv6](https://pdos.csail.mit.edu/6.828/2020/xv6.html) operating system is being ported to RV32I, and I maintain RV32I fork here: https://github.com/jserv/xv6-riscv Is it possible to run the modified xv6 on this `simple-riscv`? If so,...

Run rv32emu inside web browser via WebAssembly translation

48

[iamlouk/riscv64-sim](https://github.com/iamlouk/riscv64-sim) is written in C and capable of being translated into WebAssembly. Check its [web demo](https://louknr.net/projs/riscv64-sim/www/). Some web-based (open source) RISC-V simulations: * [WebRISC-V](https://github.com/Mariotti94/WebRISC-V): 5-stage Graphical Pipeline 32/64-bit Simulator *...

Recently, [RISC-V Architecture Test SIG](https://lists.riscv.org/g/sig-arch-test) refines the build system and introduces [RISC-V Compatibility Framework](https://riscof.readthedocs.io/en/latest/) (RISCOF) which enables testing of a RISC-V target (hard or soft implementations) against a standard RISC-V...

Synchronize with recent CoreMark

1

It has been a long time since last source adaptation of [eembc/coremark](https://github.com/eembc/coremark). Directory [sw/coremark](https://github.com/kuopinghsu/srv32/tree/master/sw/coremark) contains an old copy, and it would be nice to use git submodule to synchronize with...

Build failed on Apple M1

1

I attempted to build this project on Apple M1 powered MacBook. ```shell clang main.c -I./src -Os -Wno-inline-asm -fPIC -o interp ``` Clang complained as following: ``` In file included from...

Quote from [Arm website](https://developer.arm.com/Architectures/Scalable%20Vector%20Extensions): > Scalable Vector Extension (SVE) is a vector extension the A64 instruction set of the Armv8-A architecture. Armv9-A builds on SVE with the SVE2 extension. Unlike...