Guy Hutchison

The test in question fails because the numPools parameter is set to 2, which is the only value for which the test fails. While numPools == 1 is special cased...

They are functionally identical to a single-entry queue, however their timing characteristics are very different. The Queue module does not close timing on any of its outputs -- enq_ready and...

I'm still coming up to speed on Chisel, I can easily change the naming for the input and outputs. The producer/consumer naming convention comes from the original verilog designs (https://github.com/hutch31/sdlib)....

I generated a single-entry queue and looked at the implementation, with pipe=true it is equivalent in timing performance, so I replaced DCOutput by extending the Queue class. I also looked...

I replaced the assignments with a define which defaults to null, which should fit the bill.

I'd also like to see generating Verilog output added to the template, since it's ultimately something that every project will need to do, and the canonical way to generate Verilog...