Add Main Method to Generate Verilog

[seldridge]

Proposal to add a main that will generate Verilog into a target directory.

I'm finding that I always add this whenever I clone chisel-template and it's likely reasonable to just include this upstream.

[edwardcwang]

When I started using Chisel, a side effect of not having this was that it forced me to write tests to generate hardware...

[seldridge]

That's a good point. Gating (by default) Verilog generation on tests having passed would be safer. However, I think it's an anti-pattern to go diving through test_run_dir to find the generated Verilog. Or: that's the issue that I'm trying to address here.

[hutch31]

I'd also like to see generating Verilog output added to the template, since it's ultimately something that every project will need to do, and the canonical way to generate Verilog in Chisel seems to change relatively often.

[kazutomo]

It would be really convenient to have a code that generates Verilog, as this is always a confusing aspect of Chisel and people need it.

[Martoni]

I proposed a PR with it : https://github.com/chipsalliance/chisel-template/pull/126