tv80
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Delays in assignments
There are many #1 delays in the assignments. I think that number is arbitrary, and it doesn't help with synthesis nor simulation. I have used this core removing those statements here. If these assignments were removed in the original repository, I could just point to it (using git submodule) rather than copying the files.
Could you remove the assignments? If you prefer it, I could make a pull request for this.
I replaced the assignments with a define which defaults to null, which should fit the bill.