Guy Hutchison

Internal error when running test

1

### What is the current behavior? When running a newly created test, I receive an internal error from firrtl generation ### What is the expected behavior? Generation should complete correctly...

Added blocks for input, output, and input-output timing closure

8

Created two Chisel blocks for timing closure. These blocks are designed for use in decoupled IO designs, to make closing timing on module boundaries easier.

Chiseltest fails with None.get on zero-width literal

1

When running a test with a Bundle with zero-width elements, a fatal None.get error message is reported. This Scastie reproduces the issue: https://scastie.scala-lang.org/hutch31/lV9nKmAWRluQ4YTPI2EZ0A/10 @jackkoenig reported that: I think the issue...

[SV] Add option to generate ram blocks without x assigns

1

Generated ram blocks have an output assignment which assigns the read port value to X when read is not enabled. This can cause problems with some design flows or tools....