Compatibility for record port types (name mangling), for e.g. post synth test benchs

[donnie-j]

Hi Tristan,

Thanks again for the fixes to the demux. That has allowed us to take a look at both ilang and verilog dumps from Yosys. I would like to raise the issue of consistently name mangling for module interfaces... especially in the case of record ports.

I see that ghdlsynth is at the moment squashing record types to simple bit vectors of the same name. I admit I cannot immediately think of an optimization that breaks this while not breaking simple bit vector ports... but I still wonder if we might be better with more sophisticated name mangling.

At the very least, we will need some way to make a wrapper to allow the running of post-synthesis netlists using the RTL test benches in GHDL.

Also necessary is a write_vhdl pass from yosys... if no one is doing that, I will look at it.

[tgingold]

Adding a write_vhdl would be very nice. That's also something I'd like to use and until now I worked around because the priority was not high enough.

If you simply use ghdl --synth, it will generate a vhdl output (corresponding to the input for yosys), and in particular it generates the wrapper that vectorizes/unvectorizes records and arrays. So the code to generate wrappers is done, it just needs to be slightly adapted once the write_vhdl pass is written in yosys.