f4pga-arch-defs

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Added a section on channel wire modeling.

2

stefannikolicns

This PR adds support for multipliers and RAMs (as individual cells) from ASSPL and ASSPR in PP3e.

mkurc-ant

I have created some basic tests for DSP48E1.

2

Please review these tests and convey to me if there are any issues.

AjinkyaRaghuwanshi

QuickLogic: upstream new qlf k6n10 device

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This PR is based on top of #2137 and #2139 it requires a rebase once they are merged. This PR adds the new qlf k6n10 device

acomodi

Update README.md

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Update CMake installation required.

Dexdd

Add utility tool for generating prototype files for new primitives

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This PR adds the **build_primitive_proto** script that can be used for generating prototypes of the pb_type / model / cell_[sim|map] module from segbits and site definitions

tmichalak

Fixed support for PLLE2_BASE

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~Attempt to solve https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1991. Expecting CI to fail for now due to `BUFHCE` handling in fasm2bels.~ This PR fixes the incorrect `PLLE2_BASE` techmap (https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1991) plus updates the `prjxray-db` so that...

mkurc-ant

This PR adds: * support for nexys_video in litex tests * litesata example for nexys video board Depends on: * https://github.com/SymbiFlow/symbiflow-arch-defs/pull/2003 * https://github.com/litex-hub/litex-boards/pull/171

kowalewskijan

WIP: Add support for new Vivado 2020.2 image.

1

litghost

toolchain: yosys: add possibility to assign frontend

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Signed-off-by: Alessandro Comodi This PR adds the possibility to instruct yosys on which kind of frontend to use to parse input files. https://github.com/SymbiFlow/symbiflow-examples/issues/113 shows that there are some riscv CPU...

acomodi