f4pga-arch-defs
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f4pga
Fixed support for PLLE2_BASE
~Attempt to solve https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1991. Expecting CI to fail for now due to BUFHCE handling in fasm2bels.~
This PR fixes the incorrect PLLE2_BASE techmap (https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1991) plus updates the prjxray-db so that the most recent version is used.
Vendor tool tests (Vivado) fails on the PLL test with:
ERROR: [DRC PLCR-1] Placement Constraints Check for Clock Region(s): Design Check found an error in Clock Region X0Y0. This clock region has 14 clocks locked whereas only 12 clocks can be routed per clock region. The cells were either constrained through Area Groups or locked via user constraints. This situation can be resolved by unlocking some cells from the user constraints so that there are only 12 clocks in this region.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
This is due to missing correct BUFHCE route-through handling in fasm2bels.
I'll try to limit the number of output clocks from the PLL in the test design. This should mitigate the problem.
The BUFHCE route-through was fixed in fasm2bels some time ago. I've rebased this PR.
:/ Looks like there are some conflicting bits in the prjxray-db related to routing around PLL:
prjxray.fasm_assembler.FasmInconsistentBits: FASM line "CMT_TOP_R_UPPER_T_X8Y44.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1" wanted to clear bit (4194461, 74, 0) but was set by FASM line "CMT_TOP_R_UPPER_T_X8Y44.PLL_CLK_FREQ_BB0_NS_ACTIVE"
@mkurc-ant This should have been fixed with https://github.com/SymbiFlow/prjxray/pull/1692, I guess that the prjxray-db conda package needs a bump.
@acomodi Thanks, I've just done that. I was under impression that we used the most recent one on master.
Hmm, after rebasing which removed the fixed version of prjxray-db package the bit conflict came back again.
Right, the fact is that now, conda_lock.yml is used to build the environment, and this is generated by the conda bot updater. The environment.yml file is used as a guide for the conda bot updater to know which packages to check. I believe that for the time being you can grab the correct package from here https://github.com/SymbiFlow/symbiflow-arch-defs/pull/2251/files# and update the conda-lock file manually.
For some reason Vivado fails the RTRES-2 DRC check in kokoro even though the check is explicitly disabled in the runme script. This happens for the picosoc test on xc7a200t. The same test target succeeds when run locally.
[312/357] Generating picosoc_nexys_video_50/artix7_200t-xc7a200t-virt-xc7a200t-test/design_picosoc_nexys_video_50_vivado.bit.fasm
FAILED: cd /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7a200t-vendor/build/tests/9-soc/picosoc/picosoc_nexys_video_100/artix7_200t-xc7a200t-virt-xc7a200t-test && /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7a200t-vendor/env/conda/envs/symbiflow_arch_def_base/bin/cmake -E remove -f picosoc_nexys_video_100/artix7_200t-xc7a200t-virt-xc7a200t-test/design_picosoc_nexys_video_100_vivado.dcp && /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7a200t-vendor/env/conda/envs/symbiflow_arch_def_base/bin/cmake -E remove -f picosoc_nexys_video_100/artix7_200t-xc7a200t-virt-xc7a200t-test/design_picosoc_nexys_video_100_vivado.xpr && /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7a200t-vendor/third_party/prjxray/utils/vivado.sh -mode batch -source /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7a200t-vendor/build/tests/9-soc/picosoc/picosoc_nexys_video_100_vivado_runme.tcl > /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7a200t-vendor/build/tests/9-soc/picosoc/picosoc_nexys_video_100/artix7_200t-xc7a200t-virt-xc7a200t-test/vivado.stdout.log
ERROR: [DRC RTRES-2] Global clock nets are using local routing resources: Global clock nets are using local routing resources. 1 net(s) have at least one node with COST_CODE_NAME equal to BOUNCEACROSS or INTENT_CODE_NAME equal to NODE_DOUBLE, NODE_HLONG, NODE_HQUAD, NODE_SINGLE, NODE_VLONG, or NODE_VQUAD. This situation occurs when a global clock net must enter a clock region where all global clock routing resources are occupied. Check the report from report_clock_utilization to determine which clock regions are traversed by the problem net and use floorplanning or other physical constraints to ensure a maximum of 12 global clock nets occupy each clock region. The problem net(s) are soc.simpleuart.clk.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
