f4pga-arch-defs
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toolchain: yosys: add possibility to assign frontend
Signed-off-by: Alessandro Comodi [email protected]
This PR adds the possibility to instruct yosys on which kind of frontend to use to parse input files.
https://github.com/SymbiFlow/symbiflow-examples/issues/113 shows that there are some riscv CPU implementation that have non standard verilog files for which the frontend type cannot be guessed by yosys (SERV core).
This PR assigns a default frontend (i.e. verilog) that can be overridden with the -f|-frontend
flag in the toolchain wrappers.
I am unsure as well here actually. I don't think there is a way to specify the frontend for each single file in the list of input files.
Another solution would be to add .vh
(verilog header) files to the list in yosys directly.