Firtool error occurs when looking up parameters from a definition of a Module with reset

[unlsycn]

Type of issue: Bug Report

Please provide the steps to reproduce the problem: This code comes from the example in the documentation and simply use Module instead of RawModule.

import chisel3._
import chisel3.experimental.hierarchy.{Definition, instantiable, public}

@instantiable
class AddOne(val width: Int) extends Module {
  @public val width = width
  @public val in  = IO(Input(UInt(width.W)))
  @public val out = IO(Output(UInt(width.W)))
  out := in + 1.U
}

class Top extends Module {
  val definition = Definition(new AddOne(10))
  println(s"Width is: ${definition.width}")
}

What is the current behavior? The Chisel code runs with correctly fetched the width, but firtool gets a error:

Width is: 10
Exception in thread "main" circt.stage.phases.Exceptions$FirtoolNonZeroExitCode: firtool returned a non-zero exit code. Note that this version of Chisel (6.4.0) was published against firtool version 1.62.0.
------------------------------------------------------------------------------
ExitCode:
1
STDOUT:

STDERR:
Top.scala:6:2: error: a port "reset" with abstract reset type was unable to be inferred by InferResets (is this a top-level port?)
@instantiable
 ^
Top.scala:6:2: note: the module with this uninferred reset port was defined here

------------------------------------------------------------------------------

What is the expected behavior? Firtool doesn't encounter any errors since the Definition is not instantiated, and the reset inferring happens on Instance.

Please tell us about your environment:

• Chisel version: 6.4.0
• CIRCT version: both 1.62.0 and 1.76.0 have the same problem
• OS: Linux 6.9.0 x86_64

Other Information

What is the use case for changing the behavior?