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I have a module and test below that uses module initialization value which works and tests fine under chiseltest but when ported over to ChiselSim, it started to fail. ```scala...

carlosedp

[ChiselSim] ChiselEnum does not provide peek/poke methods and user-friendly API

4

While rewriting some tests from chiseltest to ChiselSim, I've noticed ChiselEnum is not handled by the Peek/Poke API. In a test with `c.io.inst.peek() should be(inst)` where `inst` is a `ChiselEnum.Type`,...

carlosedp

ChiselSim Improvements I started porting some tests from chiseltest to ChiselSim and found some usability gaps that could be improved. Also some error: - [ ] Having a simulator which...

carlosedp

[ChiselSim] Add expose/observe methods to simulator for submodule drilling

1

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [x] Did you delete...

carlosedp

Add a raw API for DPI intrinsics

4

Not ready for review yet but this PR adds a raw API for DPI intrinsics and demonstrates usage. The test passes locally but requires a new version of firtool. ###...

uenoku

[ChiselSim] Implement a parametric simulator able to customise simulations

1

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [x] Did you delete...

rameloni

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** Consider the following Chisel: ```scala //> using scala "2.13.12" //> using dep "org.chipsalliance::chisel:6.4.0" //> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"...

jackkoenig

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** Having a simple module containing any `Analog` port, generates an error when testing with ChiselSim. **What is...

carlosedp

Publish chisel3.std

5

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [ ] Did you add at least one test demonstrating the PR? - [x] Did you...

ZenithalHourlyRate

Change the way that Chisel IR creates registers to move these outside of when blocks. This works towards a world where the only statements allowed under FIRRTL when blocks are...

seldridge