Ben Sampson
Ben Sampson
Consider the following the use of a macro below which is valid syntax regardless of how the macro is interpreted. Verible-verilog-format says there a syntax error here when there's not....
This is a valid way to use a define but verible-verilog-format things there is a syntax error here. **Test case** ```systemverilog `define DLY #10ps module verible_sandbox ( input logic clk,...
verible_verilog_format thinks there are lexical differences between output and input when always @* statement has whitespace inside the parentheses (i.e. `always @( * )` vs `always @(*)`). Whitespace shouldn't matter...
SystemVerilog allows both ANSI and non-ANSI style port declarations, however verible-verilog-format falsely throws syntax errors for some port types when using non-ANSI style port declarations. It seems to be ok...
When using the module_net_variable_alignment flag set to 'align', it doesn't handle formatting properly (in my opinion) when there are mixed net declarations and assignments. Just because it doesn't find an...
I've been playing around with SyntaxTree and SyntaxPrinter and noticed some weird behavior where it doesn't print the port identifier correctly and instead replaces it with "unsigned long long". Not...
Clock divider Specialized adders/multipliers Async fifo Parameterized mux Reset Synchronizer Sequence detectors Cache controller Microprocessor