False syntax error for some types when using non-ANSI style port declarations

[bensampson5]

SystemVerilog allows both ANSI and non-ANSI style port declarations, however verible-verilog-format falsely throws syntax errors for some port types when using non-ANSI style port declarations. It seems to be ok with perhaps the most commonly used types such as wire, wor, wand, reg, and logic, but fails for integer, time, bit, byte, shortint, int, longint, shortreal, real, and realtime. However, it accepts those previously failing types when using ANSI-style port declarations. I haven't tested other port directions such as output or inout and I also haven't tested other constructs that are also allowed to have non-ANSI headers such as programs, interfaces, and UDPs (at least that's all that I can think of...).

I tested this using verible-verilog-format version:

v0.0-2135-gb534c1fe
Commit  2022-04-07 12:23:30 -0700
Built   2022-04-07T19:52:54Z

Test case 1 (fails) - Non-ANSI style port declarations

module test_case1 (a, b, c, d, e, f, g, h, i, j, k, l, m, n, o);

    // 4-state types
    input wire a;
    input wor b;
    input wand c;
    input reg d;
    input logic e;
    input integer f;
    input time g;

    // 2-state types
    input bit h;
    input byte i;
    input shortint j;
    input int k;
    input longint l;
    input shortreal m;
    input real n;
    input realtime o;

endmodule

Test case 2 (passes) - ANSI-style port declarations

module test_case2 (
    // 4-state types
    input wire a,
    input wor b,
    input wand c,
    input reg d,
    input logic e,
    input integer f,
    input time g,

    // 2-state types
    input bit h,
    input byte i,
    input shortint j,
    input int k,
    input longint l,
    input shortreal m,
    input real n,
    input realtime o
);

endmodule

verible-verilog-format test_case1.sv verible-verilog-format test_case2.sv

Test case 1 output

test_case1.sv: test_case1.sv:9:11-17: syntax error at token "integer"
test_case1.sv:10:11-14: syntax error at token "time"
test_case1.sv:13:11-13: syntax error at token "bit"
test_case1.sv:14:11-14: syntax error at token "byte"
test_case1.sv:15:11-18: syntax error at token "shortint"
test_case1.sv:16:11-13: syntax error at token "int"
test_case1.sv:17:11-17: syntax error at token "longint"
test_case1.sv:18:11-19: syntax error at token "shortreal"
test_case1.sv:19:11-14: syntax error at token "real"
test_case1.sv:20:11-18: syntax error at token "realtime"

Citations to published style guides would help.