Can't format assignment with macro

[bensampson5]

This is a valid way to use a define but verible-verilog-format things there is a syntax error here.

Test case

`define DLY #10ps

module verible_sandbox (
    input  logic clk,
    input  logic aresetn,
    input  logic d,
    output logic q
);

    always_ff @(posedge clk or negedge aresetn) begin
        if (!aresetn) q <= '0;
        else q <= `DLY d;
    end

endmodule

Include any options or configuration used.

Actual output

Fails.

Include any possible diagnostic messages from the formatter.

verible_sandbox/verible_sandbox.sv: verible_sandbox/verible_sandbox.sv:12:24: syntax error at token "d"

Citations to published style guides would help.