Andrew Butt

> OK! Let's get concrete about what you will measure, though: is it the number of BRAMs? Or some latency number? I'm just not sure what the quantity is that...

Yeah I definitely know the frustrations of memory in Vivado HLS. My hope is that our initial benchmarks will be simple enough (straight array partitioning or 2 banks with arbitration)...

> In general, the access patterns for the routing import step should be: > > * index lookups that SQLite should be caching already > > * Row scans that...

> I just checked the 3 indicies that get hit by the queries you listed, and they total about ~120 MB of b-trees. I believe if you try setting the...

> Which graph is this on? arty-swbut

@litghost is there any reason this pull request hasn't been merged other than a rebase? I have recently run into the issue with LDCEs being generated instead of LDCE_ZINIs and...

> I don't remember, but I believe this was not enough for LDCE support. In general, latches are not something that should be present in pure FPGA designs, so we...

@cederom #1534 has some initial work on supporting Spartan-7 parts in prjxray, but it has not yet been completed. Also, support would have to be added to symbiflow-arch-defs if you...

Yeah I realized after I wrote this that there is still ongoing work to get Calyx running on xilinx fpgas. I eventually want to run on real FPGAs, but I...

Closing for now while the xilinx flow is still in development, will reopen if it is still relevant in the future.