Add techmap for LDCE

[rw1nkler]

This commit adds missing LDCE latch techmap. The Xilinx documentation of the primitive is available in [HERE]

[andrewb1999]

@litghost is there any reason this pull request hasn't been merged other than a rebase? I have recently run into the issue with LDCEs being generated instead of LDCE_ZINIs and this seems to be the solution.

[litghost]

@litghost is there any reason this pull request hasn't been merged other than a rebase? I have recently run into the issue with LDCEs being generated instead of LDCE_ZINIs and this seems to be the solution.

I don't remember, but I believe this was not enough for LDCE support. In general, latches are not something that should be present in pure FPGA designs, so we haven't prioritized implementing support for them. Are you confident that your design should contain latches?

[andrewb1999]

I don't remember, but I believe this was not enough for LDCE support. In general, latches are not something that should be present in pure FPGA designs, so we haven't prioritized implementing support for them. Are you confident that your design should contain latches?

I am definitely not convinced that the design should have latches, but they are inferred by yosys. Is there something I should be doing to prevent yosys from inferring them?

[litghost]

I don't remember, but I believe this was not enough for LDCE support. In general, latches are not something that should be present in pure FPGA designs, so we haven't prioritized implementing support for them. Are you confident that your design should contain latches?

I am definitely not convinced that the design should have latches, but they are inferred by yosys. Is there something I should be doing to prevent yosys from inferring them?

Latches occur when you improperly define the process/state transition. I'm not an expert in HDL, here is an article that speaks to this kind of thing: https://www.nandland.com/articles/how-to-avoid-transparent-latches-in-vhdl-and-verlog.html

Tutorial - How to avoid Latches in your FPGA

Learn how to avoid creating latches by accident. Latches are almost always bad to use in your FPGA design, avoid them!